In a large scale integration (LSI), as the degree of integration and the capacity are increased, the circuit size required for a semiconductor device has been gradually narrowing. In the manufacture of the semiconductor device, a pattern is exposed and transferred onto a wafer by a reduced projection exposure apparatus generally called a stepper or scanner to form a circuit, using an original image pattern (meaning a mask or a reticle and hereinafter collectively referred to as a mask) formed with a circuit pattern, whereby the semiconductor device is manufactured.
Enhancement of yield is essential, as the manufacture of LSI involves a large manufacturing cost. Meanwhile, recent typical logic devices are under such a condition that the formation of a pattern with a line width of several ten nm is required. In these circumstances, shape defects of a pattern of a mask constitute a major cause of reduction in the yield. More specifically, the shape defect of the mask pattern includes, for example, roughness of the pattern edge (edge roughness), a line width abnormality in the pattern, and a gap abnormality between a target pattern and a pattern adjacent thereto due to pattern positional deviation.
Along with miniaturization of an LSI pattern dimension formed on a semiconductor wafer, the size of the pattern defect of a mask is also miniaturized. The dimensional accuracy of the mask is enhanced, whereby the deviation of the process terms and conditions is to be absorbed, and thus, in the inspection of a mask, an extremely small pattern is required to be detected. As a result, high inspection accuracy is required of an apparatus, which evaluates a pattern of a mask used for transfer in the manufacture of LSI. As seen in Patent document 1 (U.S. Pat. No. 4,236,825) an Inspection Apparatus for detecting a fine defect on a mask is disclosed.
Recently, as a technique for forming a fine pattern, nanoimprint lithography (NIL) has attracted attention. In this technique, a mold (die) having a nanoscale microstructure is pressure applied to a resist on a wafer to form the fine pattern on the resist.
In the nanoimprint technology, to increase productivity, a plurality of duplicate templates (replica templates) is produced using a master template as an original plate, and each replica template is mounted in different nanoimprint apparatuses during use. The replica template is required to be produced so as to accurately correspond to the master template. Thus, high inspection accuracy is required when the master template is evaluated. Further, high inspection accuracy is also required when the replica template is evaluated.
A mask is generally formed to have a size four times larger than a circuit size. A pattern is reduced and exposed onto a resist on a wafer by a reduced projection exposure device, using this mask, and thereafter, the pattern is developed to thereby form a circuit pattern of a semiconductor. Meanwhile, a template in nanoimprint lithography is formed to have a size the same as the circuit size. Thus, a shape defect in a pattern of the temperate has a higher degree of influence on a pattern to be transferred onto the wafer than the shape defect in the pattern of the mask. Accordingly, a pattern defect of the template is required to be evaluated with higher accuracy than the evaluation of the pattern defect of the mask.
However, these days when a circuit pattern is being miniaturized, the pattern size is becoming more minute than the resolution of an optical unit in a pattern evaluation apparatus. For example, in a dense pattern in which a line width of the pattern formed on a template is not more than 40 nm, the pattern cannot be resolved by a light source using DUV (Deep Ultraviolet radiation) light being 190-200 nm, even though this DUV light is easily created by an optical unit. Thus, although a light source using EB (Electron Beam) is used, throughput is low, and a problem arises in that the light source cannot be mass-produced.
The present invention has been made in consideration of the above points. Namely, this invention provides a pattern evaluation method and a pattern evaluation apparatus, which can evaluate a fine pattern with high accuracy without inducing reduction in throughput.
Other challenges and advantages of the present invention are apparent from the following description.